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From: Laurent Vivier: Subject: Re: [Qemu-devel] [PATCH] target-ppc: Multiple/String Word alignment exception: Date: Thu, 31 Mar 2016 02:53:54 +0200
 Appendix F. PowerPC Instructions. PowerPC Instructions: Mnemonic: Instruction: Format: lswi: Load String Word Immediate: X: 31: 597: lswx: Load String Word 
 Balance of Power: Introducing PowerPC Assembly Language Dave Evans. Do not use the load or store string instructions (lswi, lswx, stswi, and stswx) 
 All classic PowerPC integer instructions (for example, arithmetic, logical, load/store, and branch) are supported on e500 except lswi, lswx, stswi, 
 This patch implements the lwarx/ldarx hint bit for bit locks. Signed-off-by: Anton Blanchard <an@samba.org> ---
 Для PowerPC Processing Unit таких как STSWI, LSWI. Для PowerPC Processing Unit (PPU) теперь используется LLVM 4.0. 
 Powerpc documentation for convenient reference. BIN powerpc/powerpc/pds.twi.tudelft.nl/vakken/in101/labcourse/instruction-set/lswi-1.gif; BIN powerpc 
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 Create a new header that becomes a single location for defining PowerPC opcodes used by code that is either generationg instructions at runtime (fixups, debug, etc 
 Delete when you've had your fun ----- \ Cheap and nasty one-note assembler to test 'lswi' "Load String \ Word Immediate" Will you buy a PowerPC-based Mac when it 
 If the processor is in little-endian mode, an alignment interrupt must occur for the following instructions: lmw, stmw, lswi, lswx, stswi or stswx.
 If the processor is in little-endian mode, an alignment interrupt must occur for the following instructions: lmw, stmw, lswi, lswx, stswi or stswx.
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 Replacing the microcoded instructions with PowerPC instructions not only avoids stalling but lhau lhaux lm lmw lsi lswi mr. mullw. muls . neg. nor. or 
 Cort raised the issue of "64-bit bridge" instructions (whatever that is -- from context, 32-bit only insns that are still valid in 64-bit mode for compatibility). His 

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