--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:17:49 01/13/2017
-- Design Name:
-- Module Name: C:/Users/andreaskuk/VHDL/Task1/test.vhd
-- Project Name: Task1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: truth_table
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY test IS
END test;
ARCHITECTURE behavior OF test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT truth_table
PORT(
A : IN std_logic;
B : IN std_logic;
C : IN std_logic;
D : IN std_logic;
O : OUT std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic := '0';
signal B : std_logic := '0';
signal C : std_logic := '0';
signal D : std_logic := '0';
--Outputs
signal O : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
-- constant <clock>_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: truth_table PORT MAP (
A => A,
B => B,
C => C,
D => D,
O => O
);
-- Clock process definitions
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
c <= '1';
wait for 100 ns;
d <= '1';
wait;
end process;
END;
